Over the last few decades, the electronics industry has undergone a revolution in fabricating miniaturized and highly integrated semiconductor devices. The most common semiconductor device is a metal oxide semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor generally comprise a semiconductor substrate on which a gate electrode is disposed. The gate electrode is typically a heavily doped conductor having uniform conductivity. An input signal is typically applied to the gate electrode via a gate terminal. Heavily doped source/drain regions are formed in the semiconductor substrate and are connected to source/drain terminals. The typical MOS transistor is symmetrical, in that the source and drain regions are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device, e.g., PMOS or NMOS. A channel region is formed in the semiconductor substrate beneath the gate electrode and separates the source/drain regions. The gate electrode is generally separated from the semiconductor substrate by an insulating layer, e.g., an oxide layer, to prevent current from flowing between the gate electrode and the source/drain regions or channel regions.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electrical field is set up in the channel region. By varying the transverse electric field between the source and drain regions, it is possible to modulate the conductance of the channel region between the source and drain regions. In this manner, an electric field controls the current flow through the channel region. This type of devices is commonly referred to as a MOSFET.
In MOSFET devices, the voltage potentials of an operative transistor create a number of capacitance loads which adversely affect transistor performance. Among the capacitance loads developed in a MOSFET, an overlap capacitance is normally observed between the gate electrode and an adjacent drain region. The overlap capacitance is a function of the extent of overlap between the gate electrode and the underlying drain region as well as the thickness of the gate oxide layer. The overlap capacitance contributes to noise and tends to reduce the switching speed of the transistor, both of which are undesirable from a performance standpoint.
Various approaches have been proposed to reduce the vertical electric field effect and overlap capacitance. According to the method disclosed in U.S. Pat. No. 5,804,496 issued to Michael Duane, a gate electrode is formed by multiple ion implantation steps to reduce the conductivity of both edge portions or to dope the edge portions with a different conductivity than the central portion of the gate electrode. As shown in FIG. 1, an oxide layer 12 is formed on a substrate 10, and a gate electrode 14 is formed on a oxide layer 12. As shown in FIG. 2, ion implantation is then conducted, as indicated by arrow A, to form shallow source/drain extension 20 extending under the gate electrode 14 at a predetermined distance, which is a primary factor in the overlap capacitance of conventional semiconductors. As shown in FIG. 3, an edge dopant is implanted into the first edge portion 30 of the gate electrode 14 at a predetermined angle, as shown by arrow B. Subsequently, the second edge portion 40 is also ion implanted with the edge dopant at the predetermined angle, as shown by arrow C in FIG. 4. A spacer layer 50 is then formed on the surface of the substrate 10 including gate electrode 14, as shown in FIG. 5. Sidewall spacers 60 are then formed on the side surfaces of gate electrode 14, as shown in FIG. 6. Then, a gate dopant is ion implanted as shown by arrows D in FIG. 7, into gate electrode 14 including edge portions 30 and 40, and to form source/drain regions 70. The edge portions 30 and 40 of the gate electrode 14 contain the edge dopant which either inhibits diffusion of the gate dopant or has a different conductive type than the gate dopant. Therefore, gate dopant implantation, the edge portions 30 and 40 have reduced conductivity. Advancing to FIG. 14, the edge dopant profile of Duane's gate electrode is shown by curve N, and an actual gate impurity profile after the gate dopant implantation is shown by curve B. The gate dopant concentration level at the edge portions G.sub.D -D.sub.G and S.sub.G -G.sub.S is lower than the central portion D.sub.G -S.sub.G of Duane's gate electrode, thereby reducing the overlap capacitance formed between the edge portions 30, 40 and the source and drain regions 70. It is known that such overlap capacitance degrades the device speed, but the overlap capacitance formed between the gate electrode and source region dose not adversely impact device speed. In addition, as shown in FIG. 14, the significantly reduced amount of the gate dopant at both side portions of the gate electrode weakens the transverse electrical field in the channel region.
Accordingly, there exists a need for a semiconductor device exhibiting reduced overlap capacitance, and an efficient and production worthy method for manufacturing such a semiconductor device.